1. Field of the Invention
The present invention relates to digital logic circuits. More particularly, the present invention relates to arithmetic logic circuits and to fast lookahead carry circuits.
2. The Prior Art
Adder circuits include provision for producing and propagating a carry bit. A single bit stage of a prior-art ripple-carry adder is shown in FIG. 1. Input terms “a” and “b” are presented on input lines 10 and 12 to XOR gate 14. The “b” input on line 12 is also presented to the “0” input of multiplexer 16. A carry input (ci) on line 18 is presented to the “1” data input of multiplexer 16. The output of XOR gate 14 produces a term px that is used to drive the select input of multiplexer 16. The output of multiplexer 16 is the carry output of the adder presented on carry-out line (co) 20. The px term and the ci input (shown as the cx input) are presented to XOR gate 22. The output term of the adder is presented on line 24 at the output of XOR gate 22. The carry chain is the portion of the circuit of FIG. 1 contained within the dashed lines 26 of FIG. 1.
Different prior-art adder types use the same logic to create the carry-propagate signal px for a bit x as well as the carry input signal ux, and the XOR gate 22 to create the sum output(s) from the propagate signal px and the local carry output signal cx.
FIGS. 2-8 focus on alternative implementations of the carry-chain logic between ci, px and ux inputs and co and cx outputs of the carry chain, contained within the dashed lines 26 of FIG. 1, in order to compare the prior art with the present invention. FIGS. 2-8 show different examples of multi-bit adders.
FIG. 2 is a schematic diagram of a carry chain of a prior-art 2-bit wide ripple-carry adder. The carry-input signal u0 for bit 0 is presented on line 30 to the “0” input of multiplexer 32. The carry-in signal ci is presented on line 34 to the “1” input of multiplexer 32. The propagate signal p0 for bit 0 is presented on line 36 to the select input of multiplexer 32.
The carry-input signal u1 for bit 1 is presented on line 38 to the “0” input of multiplexer 40. The output of multiplexer 32 is presented to the “1” input of multiplexer 40. The propagate signal p1 for bit 1 is presented on line 42 to the select input of multiplexer 40. The output of multiplexer 40 is buffered by buffer 44 to produce the carry-out (co) signal on line 46. The carry-in signal on line 34 is buffered by buffer 48 to produce the local carry-out signal c0 on line 50. The output of multiplexer 32 is buffered by buffer 52 to produce the local carry-out signal c1 on line 54.
The buffer 44 at the carry output is optional and could alternatively be an inverter, creating an inverted carry-output and it can be placed after any number of multiplexers to optimize speed. The other buffers 48 and 52 are also optional, and serve to limit the capacitive load on the main carry path.
Referring now to FIG. 3, a schematic diagram shows only the carry chain of a prior-art 2-bit wide carry-lookahead-adder. The carry-input signal u0 for bit 0 is presented on line 60 to the “0” input of multiplexer 62. The carry-in signal ci is presented on line 64 to the “1” input of multiplexer 62. The propagate signal p0 for bit 0 is presented on line 66 to the select input of multiplexer 62.
The carry-input signal u1 for bit 1 is presented on line 68 to the “0” input of multiplexer 70. The output of multiplexer 62 is presented to the “1” input of multiplexer 70. The propagate signal p1 for bit 1 is presented on line 72 to the select input of multiplexer 70. The output of multiplexer 70 is buffered by buffer 74.
The output of buffer 74 is presented to the “0” input of multiplexer 76. The carry-in input ci is presented to the “1” input of multiplexer 76. The propagate signals p0 and p1 are combined in AND gate 78. The output of AND gate 78 is presented to the select input of multiplexer 76. The output of multiplexer 76 is buffered by buffer 80 to produce the carry-out (co) signal on line 82. The carry-in signal on line 64 is buffered by buffer 84 to produce the local carry-out c0 signal on line 86. The output of multiplexer 62 is buffered by buffer 88 to produce the local carry-out c1 signal on line 90. Buffers 74, 80, 84, and 88 are optional and buffers 80, 84, and 88 could also be inverters without having to invert any of the signals.
If both propagate signals p0 and p1 within the basic lookahead-unit (2 bits wide in this example) are logic “1,” the carry-input of the entire stage gets propagated to the co output on line 82 by multiplexer 76.
Referring now to FIG. 4, a schematic diagram shows only the carry chain of a prior-art 3-bit wide carry-lookahead-adder. The carry-input signal u0 for bit 0 is presented on line 100 to the “0” input of multiplexer 102. The carry-in signal ci is presented on line 104 to the “1” input of multiplexer 102. The propagate signal p0 for bit 0 is presented on line 106 to the select input of multiplexer 102.
The carry-input signal u1 for bit 1 is presented on line 108 to the “0” input of multiplexer 110. The output of multiplexer 102 is presented to the “1” input of multiplexer 110. The propagate signal p1 for bit 1 is presented on line 112 to the select input of multiplexer 110.
The carry-input signal u2 for bit 2 is presented on line 114 to the “0” input of multiplexer 116. The output of multiplexer 110 is presented to the “1” input of multiplexer 116. The propagate signal p2 for bit 2 is presented on line 118 to the select input of multiplexer 116. The output of multiplexer 116 is buffered by buffer 120.
The output of buffer 120 is presented to the “0” input of multiplexer 122. The carry-in input ci is presented to the “1” input of multiplexer 122. The propagate signals p0, p1, and p2 are combined in AND gate 124. The output of AND gate 124 is presented to the select input of multiplexer 122. The output of multiplexer 122 is buffered by buffer 126 to produce the carry-out (co) signal on line 128. The carry-in signal on line 104 is buffered by buffer 130 to produce the local carry-out signal c0 on line 132. The output of multiplexer 102 is buffered by buffer 134 to produce the local carry-out c1 signal on line 136. The output of multiplexer 110 is buffered by buffer 138 to produce the local carry-out c2 signal on line 140. Buffers 120, 126, 130 134, and 138 are optional and buffers 126, 130, 134, and 138 could also be inverters without having to invert any of the signals.
In a manner similar to the operation of the carry chain of the 2-bit wide carry-lookahead-adder of FIG. 3, if all three propagate signals p0, p1, and p2 within the basic lookahead-unit are logic “1,” the carry-input of the entire stage gets propagated to the co output on line 128 by multiplexer 122.